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PSoC(R) Mixed-Signal Array
CY8C24094, CY8C24794, CY8C24894, and CY8C24994
Features
Final Data Sheet
CY8C24894 includes an XRES pin to support In-System Serial Programming (ISSP) and external reset control Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 3.0 to 5.25V Operating Voltage Industrial Temperature Range: -40C to +85C USB Temperature Range: -10C to +85C Advanced Peripherals (PSoC Blocks) 6 Rail-to-Rail Analog PSoC Blocks Provide: - Up to 14-Bit ADCs - Up to 9-Bit DACs - Programmable Gain Amplifiers - Programmable Filters and Comparators 4 Digital PSoC Blocks Provide: - 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Full-Duplex UART - Multiple SPITM Masters or Slaves - Connectable to all GPIO Pins Complex Peripherals by Combining Blocks Capacitive Sensing Application Capability Full-Speed USB (12 Mbps) Four Uni-Directional Endpoints One Bi-Directional Control Endpoint USB 2.0 Compliant Dedicated 256 Byte Buffer No External Crystal Required Flexible On-Chip Memory 16K Flash Program Storage 50,000 Erase/ Write Cycles 1K SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO Up to 48 Analog Inputs on GPIO Two 33 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Precision, Programmable Clocking Internal 4% 24/48 MHz Oscillator Internal Oscillator for Watchdog and Sleep .25% Accuracy for USB with no External Components Additional System Resources I2CTM Slave, Master, and Multi-Master to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog Drivers
PSoC(R) Functional Overview
The PSoC(R) family consists of many Mixed-Signal Array with On-Chip Controller devices. All PSoC family devices are designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. The PSoC CY8C24x94 devices are unique members of the PSoC family because it includes a full-featured, full-speed (12 Mbps) USB port. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of industrial, consumer, and communication applications. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources including a full-speed USB port. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x94 devices can have up to seven IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks.
System Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog
CPU Core (M8C) ClockSources (Includes IMO and ILO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital 2 Decimator Clocks MACs Type 2
I2C
Internal POR and LVD Voltage System Resets Ref.
USB
Analog Input Muxing
SYSTEM RESOURCES
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The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. In USB systems, the IMO will self-tune to 0.25% accuracy for USB communication. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.
Digital peripheral configurations include those listed below.

Full-Speed USB (12 Mbps) PWMs (8 to 32 bit) PWMs with Dead band (8 to 24 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Characteristics.
The Analog System
The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.

The Digital System
The Digital System is composed of 4 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital System Block Diagram
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to 2, with selectable gain to 48x) Instrumentation amplifiers (1 with selectable gain to 93x) Comparators (up to 2, with 16 selectable thresholds) DACs (up to 2, with 6- to 9-bit resolution) Multiplying DACs (up to 2, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible

Digital Clocks FromCore
To System Bus
ToAnalog System

DIGITAL SYSTEM
Digital PSoC Block Array
Row Input Configuration 8 8
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
8 8
Row Output Configuration

GIE[7:0] GIO[7:0]
GlobalDigital Interconnect
GOE[7:0] GOO[7:0]
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Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. Analog System Block Diagram
All IO (Except Port 7) P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn Analog Mux Bus P0[6] P0[4] P0[2] P0[0] P2[6]
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 05. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

Track pad, finger sensing. Chip-wide mux that allows analog input from up to 48 IO pins. Crosspoint connection between any IO pin combinations.
P2[3]
P2[4] P2[2] P2[0]
P2[1]
When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which can be found under http://www.cypress.com >> DESIGN RESOURCES >> Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.
ACI0[1:0] ACI1[1:0]
Array Input Configuration
Additional System Resources
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21
Block Array
System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.
AnalogReference
Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Full-Speed USB (12 Mbps) with 5 configurable endpoints and 256 bytes of RAM. No external components required except two series resistors. Wider than commercial temperature USB operation (-10C to +85C). Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math as well as digital filters. Decimator provides a custom hardware filter for digital signal processing apps. including creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, multi-master are supported. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system.
M8C Interface (Address Bus, Data Bus, Etc.)

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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is shown in the highlighted row of the table PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size PSoC Part Number Flash Size
Getting Started
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. To determine which PSoC device meets your requirements, navigate through the PSoC Decision Tree in the Application Note AN2209 at http://www.cypress.com and select Application Notes under the Design Resources.
CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34
up to 64 up to 44 56 up to 24 up to 28 16 up to 28
4 2 1 1 1 1 0
16 8 4 4 4 4 0
12 12 48 12 28 8 28
4 4 2 2 0 0 0
4 4 2 2 2 2 0
12 12 6 6 4a 4
a
2K 256 Bytes 1K 256 Bytes 512 Bytes 256 Bytes 512 Bytes
32K 16K 16K 4K 8K 4K 8K
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
3b
a. Limited analog functionality. b. Two analog blocks and one CapSense.
Technical Training Modules
Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http:// www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date as default.
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Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. PSoC Designer Subsystems
PSoC Designer
Graphical Designer Interface
Context Sensitive Help
Commands
Results
Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet
PSoC Designer Core Engine
Manufacturing Information File
Emulation Pod
In-Circuit Emulator
Device Programmer
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PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework.
Debugger
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
The Design Browser allows users to select and import preconfigured designs into the user's project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
Application Editor
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.
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Designing with User Modules
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
User Module/Source Code Development Flows
Device Editor
User Module Selection Placement and Parameter -ization Source Code Generator
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build All
Debugger
Interface to ICE Storage Inspector Event & Breakpoint Manager
The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym Description
Table of Contents
For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual. This document encompasses and is organized into the following chapters and sections. 1.
Pin Information ........................................................................................ 9
AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SRAM
alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor static random access memory
1.1 1.2 1.3 1.4 1.5 1.6 1.7
2.
56-Pin Part Pinout ......................................................................... 9 56-Pin Part Pinout (with XRES) .................................................. 10 68-Pin Part Pinout ........................................................................ 11 68-Pin Part Pinout (On-Chip Debug) ........................................... 12 100-Ball VFBGA Part Pinout ........................................................ 13 100-Ball VFBGA Part Pinout (On-Chip Debug) ........................... 15 100-Pin Part Pinout (On-Chip Debug) .......................................... 17
Register Reference ................................................................................ 19 2.1 Register Conventions ................................................................... 19 2.1.1 Abbreviations Used ....................................................... 19 2.2 Register Mapping Tables ............................................................. 19 Electrical Specifications ....................................................................... 22 3.1 Absolute Maximum Ratings ......................................................... 23 3.2 Operating Temperature ................................................................ 23 3.3 DC Electrical Characteristics ........................................................ 23 3.3.1 DC Chip-Level Specifications ........................................ 23 3.3.2 DC General Purpose IO Specifications ......................... 24 3.3.3 DC Full-Speed USB Specifications ............................... 24 3.3.4 DC Operational Amplifier Specifications ....................... 25 3.3.5 DC Low Power Comparator Specifications ................... 26 3.3.6 DC Analog Output Buffer Specifications ....................... 27 3.3.7 DC Analog Reference Specifications ............................ 28 3.3.8 DC Analog PSoC Block Specifications .......................... 29 3.3.9 DC POR and LVD Specifications .................................. 29 3.3.10 DC Programming Specifications ................................... 30 3.4 AC Electrical Characteristics ........................................................ 31 3.4.1 AC Chip-Level Specifications ........................................ 31 3.4.2 AC General Purpose IO Specifications ......................... 32 3.4.3 AC Full-Speed USB Specifications ............................... 32 3.4.4 AC Operational Amplifier Specifications ........................ 33 3.4.5 AC Low Power Comparator Specifications ................... 35 3.4.6 AC Digital Block Specifications ..................................... 35 3.4.7 AC External Clock Specifications .................................. 35 3.4.8 AC Analog Output Buffer Specifications ........................ 36 3.4.9 AC Programming Specifications .................................... 37 3.4.10 AC I2C Specifications .................................................... 38 Packaging Information .......................................................................... 39 4.1 Packaging Dimensions ................................................................. 39 4.2 Thermal Impedance ..................................................................... 42 4.3 Solder Reflow Peak Temperature ................................................ 42 Development Tool Selection ................................................................ 43 5.1 Software ....................................................................................... 43 5.1.1 PSoC Designer .............................................................. 43 5.1.2 PSoC Express ............................................................... 43 5.1.3 PSoC Programmer ........................................................ 43 5.1.4 CY3202-C iMAGEcraft C Compiler ............................... 43 5.2 Development Kits ......................................................................... 43 5.2.1 CY3215-DK Basic Development Kit .............................. 43 5.2.2 CY3210-ExpressDK Development Kit ........................... 44 5.3 Evaluation Tools ........................................................................... 44 5.3.1 CY3210-MiniProg1 ........................................................ 44 5.3.2 CY3210-PSoCEval1 ...................................................... 44 5.3.3 CY3214-PSoCEvalUSB ................................................ 44 5.4 Device Programmers ................................................................... 44 5.4.1 CY3216 Modular Programmer ...................................... 44 5.4.2 CY3207ISSP In-System Serial Programmer (ISSP) ..... 44 5.5 Accessories (Emulation and Programming) ................................. 45 5.6 3rd-Party Tools ............................................................................. 45 5.7 Build a PSoC Emulator into Your Board ...................................... 45 Ordering Information ............................................................................ 46 6.1 Ordering Code Definitions ............................................................ 46 Sales and Company Information ......................................................... 47 7.1 Revision History ........................................................................... 47 7.2 Copyrights and Code Protection .................................................. 48
3.
4.
5.
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 3-1 on page 22 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal.
6. 7.
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
1.1
56-Pin Part Pinout
Name Description
Table 1-1. 56-Pin Part Pinout (QFN**) See LEGEND details and footnotes in Table 1-2 on page 10.
Type Pin No. Digital Analog 1 IO I, M 2 IO I, M 3 IO M 4 IO M 5 IO M 6 IO M 7 IO M 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 Power 20 USB 21 USB 22 Power 23 IO 24 IO 25 IO M 26 IO M 27 IO M 28 IO M 29 IO M 30 IO M 31 IO M 32 IO M 33 IO M 34 IO M 35 IO M 36 IO M 37 IO M 38 IO M 39 IO M 40 IO M 41 IO I, M 42 IO I, M 43 IO M
CY8C24794 56-Pin PSoC Device
P2[5],M P2[7],M P0[1], A, I, M P0[3], A, IO, M P0[5], A, IO, M P0[7], A, I, M Vss Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M P2[4],M A, I, M, P2[3] A, I, M, P2[1] M,P4[7] M,P4[5] M,P4[3] M,P4[1] M,P3[7] M,P3[5] M,P3[3] M,P3[1] M,P5[7] M,P5[5] M,P5[3] M,P5[1]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
Direct switched capacitor block input. Direct switched capacitor block input.
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP SCLK*. Ground connection.
Supply voltage.
I2C Serial Data (SDA), ISSP SDATA*.
Type Pin No. Digital Analog 44 IO M 45 IO I, M 46 IO I, M 47 IO I, M 48 IO I, M 49 Power 50 Power 51 IO I, M 52 IO IO, M 53 IO IO, M Direct switched capacitor block input. 54 IO I, M Direct switched capacitor block input. 55 IO M External Analog Ground (AGND) input. 56 IO M
Name
P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
February 15, 2007
Document No. 38-12018 Rev. *J
M, I2C SCL, P1[7] M, I2C SDA, P1[5] M,P1[3] M, I2C SCL, P1[1] Vss D+ DVdd P7[7] P7[0] M, I2C SDA, P1[0] M,P1[2] M,P1[4] M,P1[6]
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
QFN
(Top View )
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2[2], A, I, M P2[0], A, I, M P4[6],M P4[4],M P4[2],M P4[0],M P3[6],M P3[4],M P3[2],M P3[0],M P5[6],M P5[4],M P5[2],M P5[0],M
Description
External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input. Analog column mux input VREF. Analog column mux input. Supply voltage. Ground connection. Analog column mux input,. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
9
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.2
56-Pin Part Pinout (with XRES)
Name Description
Table 1-2. 56-Pin Part Pinout (QFN**)
Type Pin No. Digital Analog 1 IO I, M 2 IO I, M 3 IO M 4 IO M 5 IO M 6 IO M 7 IO M 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 Power 20 USB 21 USB 22 Power 23 IO 24 IO 25 IO M 26 IO M 27 IO M 28 IO M
CY8C24894 56-Pin PSoC Device
M M A, I, M A, IO, M P0[5], A, IO, M P0[7], A, I, M Vss Vdd M M M M A, A, A, A, 48 47 46 45 P0[6], P0[4], P0[2], P0[0], I, I, I, I, 44 43 P2[6], M P2[4], M
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6]
Direct switched capacitor block input. Direct switched capacitor block input.
A, I, M, P2[3] A, I, M, P2[1] M, M, M, M, M, P4[7] P4[5] P4[3] P4[1] P3[7]
1 2 3 4 5 6 7 8 9 10 11 12 13 14
56 55 54 53 52 51 50 49
P2[5], P2[7], P0[1], P0[3],
QFN
(Top View)
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP SCLK*. Ground connection.
M, P3[5] M, P3[3] M, P3[1] M, M, M, M, P5[7] P5[5] P5[3] P5[1]
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2[2], A, I, M P2[0], A, I, M P4[6], P4[4], P4[2], P4[0], XRES M M M M
P3[4], M P3[2], M P3[0], M P5[6], P5[4], P5[2], P5[0], M M M M
15 16
17 18 19 20 21 22 23 24 M, P1[3] M, I2C SCL, P1[1] Vss D+ DVdd P7[7]
M, I2C SCL, P1[7] M, I2C SDA, P1[5]
I2C Serial Data (SDA), ISSP SDATA*.
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO
M M M M M M M
P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
M M M M I, M I, M M
Type Pin No. Digital Analog 44 IO M 45 IO I, M 46 IO I, M 47 IO I, M 48 IO I, M Active high external reset with internal 49 Power pull down. 50 Power 51 IO I, M 52 IO IO, M 53 IO IO, M Direct switched capacitor block input. 54 IO I, M Direct switched capacitor block input. 55 IO M External Analog Ground (AGND) input. 56 IO M
Name
Description
P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input. Analog column mux input VREF. Analog column mux input. Supply voltage. Ground connection. Analog column mux input,. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
February 15, 2007
Document No. 38-12018 Rev. *J
M, I2C SDA, M, M, M,
P7[0] P1[0] P1[2] P1[4] P1[6]
Supply voltage.
25 26 27 28
10
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.3
68-Pin Part Pinout
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device. Table 1-3. 68-Pin Part Pinout (QFN**)
Type Pin No. Digital Analog 1 IO M 2 IO M 3 IO M 4 IO M 5 6 7 Power 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 IO M 20 Power 21 USB 22 USB 23 Power 24 IO 25 IO 26 IO 27 IO 28 IO 29 IO 30 IO 31 IO 32 IO M 33 IO M 34 IO M Name Description
CY8C24994 68-Pin PSoC Device
AI AI AI AI Ext. VREF Ext. AGND AI 55 54 53 52 M, M, M, M, M, M, M,
P4[7] P4[5] P4[3] P4[1] NC NC Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] NC NC XRES
AI AIO AIO
AI AI
M, M, M M M, M, M,
No connection. No connection. Ground connection.
M, P4[7] M, P4[5] M, P4[3] M, P4[1] NC NC Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, M, I2C SCL, M, I2C SDA, M, P5[3] P5[1] P1[7] P1[5]
68 67 66 65 64 63 62 61 60 59 58 57 56
P0[7], Vss Vdd P0[6], P0[4], P0[2], P0[0], P2[6], P2[4], P2[2],
P2[1], P2[3], P2[5], P2[7], P0[1], P0[3], P0[5],
M, AI
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL) ISSP SCLK*. Ground connection.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
QFN
(Top View)
P2[0], P4[6], P4[4], P4[2], P4[0], XRES NC NC P3[6], P3[4], P3[2], P3[0],
M, AI M M M M
M M M M
P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
18 19 20 21 22 23 24 25 26 27 M, P1[3] I2C SCL, M, P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4]
Supply voltage.
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
IO IO IO IO IO IO IO IO IO
M M M M M M M M M
Type Pin No. Digital Analog 50 IO M I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M 52 IO I,M Optional External Clock Input (EXT53 IO M CLK). 54 IO M 55 IO I,M 56 IO I,M 57 IO I,M 58 IO I,M 59 Power 60 Power 61 IO I,M 62 IO IO,M
Name
P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2. Analog column mux input and column output. Analog column mux input.
Input IO IO IO M M M
No connection. No connection. Active high pin reset with internal pull down.
63 64 65 66 67 68
IO IO IO IO IO IO
IO,M I,M M M I,M I,M
P4[0] P4[2] P4[4]
Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input. * These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
February 15, 2007
Document No. 38-12018 Rev. *J
P7[3] P7[2] P7[1] P7[0] I2C SDA, M, P1[0] M, P1[2] M, P1[4]
28 29 30 31 32 33 34
Description
11
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.4
68-Pin Part Pinout (On-Chip Debug)
The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 1-4. 68-Pin Part Pinout (QFN**)
Type Pin No. Digital Analog 1 IO M 2 IO M 3 IO M 4 IO M 5 6 7 Power 8 IO M 9 IO M 10 IO M 11 IO M 12 IO M 13 IO M 14 IO M 15 IO M 16 IO M 17 IO M 18 IO M 19 IO M 20 Power 21 USB 22 USB 23 Power 24 IO 25 IO 26 IO 27 IO 28 IO 29 IO 30 IO 31 IO 32 IO M 33 IO M 34 IO M Name Description
CY8C24094 68-Pin OCD PSoC Device
P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI
P4[7] P4[5] P4[3] P4[1] OCDE OCDO Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES
P2[3], M, AI P2[5], M P2[7], M P0[1], M, AI P0[3], M, AIO P0[5], M, AIO 66 65
P2[1], M, AI
68 67
64 63 62 61 60 59
58 57 56
I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C Serial Clock (SCL), ISSP SCLK*. Ground connection.
M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5]
55 54 53 52
OCD even data IO. OCD odd data output. Ground connection.
P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI P0[2], M, AI P0[0], M, AI
18 19
20 21 22
23 24 25 26 27
M, P1[3] I2C SCL, M, P1[1] Vss D+ DVdd
Supply voltage.
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
IO IO IO IO IO IO IO IO IO
M M M M M M M M M
Type Pin No. Digital Analog 50 IO M I2C Serial Data (SDA), ISSP SDATA*. 51 IO I,M 52 IO I,M Optional External Clock Input (EXT53 IO M CLK). 54 IO M 55 IO I,M 56 IO I,M 57 IO I,M 58 IO I,M 59 Power 60 Power 61 IO I,M 62 IO IO,M
Name
Description
P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Ground connection. Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2. Analog column mux input and column output. Analog column mux input.
Input IO IO IO M M M
OCD high-speed clock output. OCD CPU clock output. Active high pin reset with internal pull down.
63 64 65 66 67 68
IO IO IO IO IO IO
IO,M I,M M M I,M I,M
P4[0] P4[2] P4[4]
Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger. * These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
February 15, 2007
Document No. 38-12018 Rev. *J
I2C SDA, M, P1[0] M, P1[2] M, P1[4]
P7[7] P7[6] P7[5] P7[4]
P7[3] P7[2] P7[1] P7[0]
28 29 30 31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
QFN
(Top View)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
12
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.5
100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device. Table 1-5. 100-Ball Part Pinout (VFBGA)
Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
Vss Vss NC NC NC Power Vdd NC NC Power Vss Power Vss Power Vss Power Vss IO I,M P2[1] IO I,M P0[1] IO I,M P0[7] Power Vdd IO I,M P0[2] IO I,M P2[2] Power Vss Power Vss NC IO M P4[1] IO M P4[7] IO M P2[7] IO IO,M P0[5] IO I,M P0[6] IO I,M P0[0] IO I,M P2[0] IO M P4[2] NC NC IO M P3[7] IO M P4[5] IO M P2[5] IO IO,M P0[3] IO I,M P0[4] IO M P2[6] IO M P4[6] IO M P4[0] NC NC NC IO M P4[3] IO I,M P2[3] Power Vss Power Vss IO M P2[4] IO M P4[4] IO M P3[6] NC
Power Power
Ground connection. Ground connection. No connection. No connection. No connection. Supply voltage. No connection. No connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Direct switched capacitor block input. Ground connection. Ground connection. No connection.
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 Analog column mux input and column output. H5 Analog column mux input. H6 Analog column mux input. H7 Direct switched capacitor block input. H8 H9 No connection. H10 No connection. J1 J2 J3 J4 Analog column mux input and column output. J5 Analog column mux input. J6 External Voltage Reference (VREF) input. J7 J8 J9 No connection. J10 No connection. K1 No connection. K2 K3 Direct switched capacitor block input. K4 Ground connection. K5 Ground connection. K6 External Analog Ground (AGND) input. K7 K8 K9 No connection. K10
IO M IO M IO M Power Power IO M IO M IO IO IO IO IO IO IO IO IO IO M M M M M M M M
IO M IO M IO M IO M IO M IO M IO M IO M IO Power Power USB USB Power IO IO IO M Power Power Power Power
Power IO IO IO Power Power
NC P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] Vss Vss D+ DVdd P7[7] P7[0] P5[2] Vss Vss Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss
No connection.
Ground connection. Ground connection.
Active high pin reset with internal pull down. No connection.
I2C Serial Clock (SCL). I2C Serial Clock (SCL), ISSP SCLK*. I2C Serial Data (SDA), ISSP SDATA*.
No connection.
I2C Serial Data (SDA).
Ground connection. Ground connection.
Supply voltage.
Ground connection. Ground connection. Ground connection. Ground connection. No connection. No connection. Supply voltage.
Ground connection. Ground connection.
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection. * This is the ISSP pin, which is not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
February 15, 2007
Document No. 38-12018 Rev. *J
13
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
CY8C24994
1 A B C D E F G H J K
Vss
2
Vss
3
NC
4
NC
5
NC
6
Vdd
7
NC
8
NC
9
Vss
10
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
NC
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
February 15, 2007
Document No. 38-12018 Rev. *J
14
[+] Feedback
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.6
100-Ball VFBGA Part Pinout (On-Chip Debug)
The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 1-6. 100-Ball Part Pinout (VFBGA)
Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
Vss Vss NC NC NC Power Vdd NC NC Power Vss Power Vss Power Vss Power Vss IO I,M P2[1] IO I,M P0[1] IO I,M P0[7] Power Vdd IO I,M P0[2] IO I,M P2[2] Power Vss Power Vss NC IO M P4[1] IO M P4[7] IO M P2[7] IO IO,M P0[5] IO I,M P0[6] IO I,M P0[0] IO I,M P2[0] IO M P4[2] NC NC IO M P3[7] IO M P4[5] IO M P2[5] IO IO,M P0[3] IO I,M P0[4] IO M P2[6] IO M P4[6] IO M P4[0] CCLK NC NC IO M P4[3] IO I,M P2[3] Power Vss Power Vss IO M P2[4] IO M P4[4] IO M P3[6] HCLK
Power Power
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 Analog column mux input and column output. H5 Analog column mux input. H6 Analog column mux input. H7 Direct switched capacitor block input. H8 H9 No connection. H10 No connection. J1 J2 J3 J4 Analog column mux input and column output. J5 Analog column mux input. J6 External Voltage Reference (VREF) input. J7 J8 J9 OCD CPU clock output. J10 No connection. K1 No connection. K2 K3 Direct switched capacitor block input. K4 Ground connection. K5 Ground connection. K6 External Analog Ground (AGND) input. K7 K8 K9 OCD high-speed clock output. K10
Ground connection. Ground connection. No connection. No connection. No connection. Supply voltage. No connection. No connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column mux input. Analog column mux input. Supply voltage. Analog column mux input. Direct switched capacitor block input. Ground connection. Ground connection. No connection.
IO M IO M IO M Power Power IO M IO M IO IO IO IO IO IO IO IO IO IO M M M M M M M M
IO M IO M IO M IO M IO M IO M IO M IO M IO Power Power USB USB Power IO IO IO M Power Power Power Power
Power IO IO IO Power Power
OCDE P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1] OCDO P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] Vss Vss D+ DVdd P7[7] P7[0] P5[2] Vss Vss Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss
OCD even data IO.
Ground connection. Ground connection.
Active high pin reset with internal pull down. OCD odd data output.
I2C Serial Clock (SCL). I2C Serial Clock (SCL), ISSP SCLK*. I2C Serial Data (SDA), ISSP SDATA*.
No connection.
I2C Serial Data (SDA).
Ground connection. Ground connection.
Supply voltage.
Ground connection. Ground connection. Ground connection. Ground connection. No connection. No connection. Supply voltage.
Ground connection. Ground connection.
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger. * This is the ISSP pin, which is not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
CY8C24094 OCD
1 A B C D E F G H J K
Vss
2
Vss
3
NC
4
NC
5
NC
6
Vdd
7
NC
8
NC
9
Vss
10
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HClk
ocde
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Not for Production
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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.7
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 1-7. 100-Pin Part Pinout (TQFP)
Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC IO I, M P0[1] IO M P2[7] IO M P2[5] IO I, M P2[3] IO I, M P2[1] IO M P4[7] IO M P4[5] IO M P4[3] IO M P4[1] OCDE OCDO NC Power Vss IO M P3[7] IO M P3[5] IO M P3[3] IO M P3[1] IO M P5[7] IO M P5[5] IO M P5[3] IO M P5[1] IO M P1[7] NC NC NC IO P1[5] IO P1[3] IO P1[1] NC Vss D+ DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] NC NC NC NC P1[0] P1[2] P1[4]
No connection. No connection. Analog column mux input.
Direct switched capacitor block input. Direct switched capacitor block input.
OCD even data IO. OCD odd data output. No connection. Ground connection.
I2C Serial Clock (SCL). No connection. No connection. No connection. I2C Serial Data (SDA) Crystal (XTALin), I2C Serial Clock (SCL), ISSP SCLK*. No connection. Ground connection.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
IO IO IO IO IO IO IO IO IO
M M M M M M M M M
Input IO M IO M Power IO M IO M IO I, M IO I, M IO IO IO I
IO IO
I, M I, M
P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] Vss P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC
OCD high-speed clock output. OCD CPU clock output. Active high pin reset with internal pull down.
Ground connection.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. No connection. External Voltage Reference (VREF) input. No connection. Analog column mux input. No connection. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection. Analog column mux input. Supply voltage. No connection. Ground connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. No connection. Analog column mux input. No connection. Analog column mux input and column output. No connection. Analog column mux input and column output. No connection.
Power USB USB Power IO IO IO IO IO IO IO IO
Supply voltage.
IO IO IO
No connection. No connection. No connection. No connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP SDATA*. Optional External Clock Input (EXTCLK).
IO I, M P0[6] Power Vdd NC Power Vss NC NC NC NC NC NC NC NC NC NC IO I, M P0[7] NC IO IO, M P0[5] NC IO IO, M P0[3] NC
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger. * These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
CY8C24094 OCD
P0[3], M, AI NC P0[5], M, AI
NC P0[7], M, AI NC
NC Vdd P0[6], M, AI NC P0[4], M, AI
100 99
98 97 96
95 94 93 92 91
90 89 88
87 86 85 84 83 82 81
80 79 78
NC NC AI, M , P0[1] M , P2[7] M , P2[5] AI, M , P2[3] AI, M , P2[1] M , P4[7] M , P4[5] M , P4[3] M , P4[1] OCDE OCDO NC Vss M , P3[7] M , P3[5] M , P3[3] M , P3[1] M , P5[7] M , P5[5] M , P5[3] M , P5[1] I2C SCL, P1[7] NC
77 76 M,P1[2] M,P1[4]
NC P0[2], M, AI NC
NC NC Vss
NC
NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC P0[0], M , AI NC P2[6], M , External VREF NC P2[4], M , External AGND P2[2], M , AI P2[0], M , AI P4[6], M P4[4], M Vss P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
TQFP
26 27
28 29 30
31 32 33 34 35
36 37 38 39 40 41 42 43 44 45 P7[7] P7[6] P7[5] P7[4] P7[3] P7[2]
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P7[1] P7[0] NC NC NC NC I2C SDA, M, P1[0]
NC
46 47 48 49 50
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2. Register Reference
This chapter lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.
2.1
2.1.1
Register Conventions
Abbreviations Used
2.2
Register Mapping Tables
The register conventions specific to this section are listed in the following table.
Convention Description
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
R W L C #
Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
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2. Register Reference
Register Map Bank 0 Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
00 RW PMA0_DR 40 RW 01 RW PMA1_DR 41 RW 02 RW PMA2_DR 42 RW 03 RW PMA3_DR 43 RW 04 RW PMA4_DR 44 RW 05 RW PMA5_DR 45 RW 06 RW PMA6_DR 46 RW 07 RW PMA7_DR 47 RW 08 RW USB_SOF0 48 R 09 RW USB_SOF1 49 R 0A RW USB_CR0 4A RW 0B RW USBIO_CR0 4B # 0C USBIO_CR1 4C RW RW 0D 4D RW 0E EP1_CNT1 4E # RW 0F EP1_CNT 4F RW RW 10 EP2_CNT1 50 # RW 11 EP2_CNT 51 RW RW 12 EP3_CNT1 52 # RW 13 EP3_CNT 53 RW RW 14 EP4_CNT1 54 # RW 15 EP4_CNT 55 RW RW 16 EP0_CR 56 # RW 17 EP0_CNT 57 # RW 18 EP0_DR0 58 RW 19 EP0_DR1 59 RW 1A EP0_DR2 5A RW 1B EP0_DR3 5B RW 1C EP0_DR4 5C RW RW PRT7DR 1D EP0_DR5 5D RW RW PRT7IE 1E EP0_DR6 5E RW RW PRT7GS 1F EP0_DR7 5F RW RW PRT7DM2 60 20 RW DBB00DR0 # AMX_IN 61 21 DBB00DR1 W AMUXCFG RW 62 22 DBB00DR2 RW 63 23 RW DBB00CR0 # ARF_CR 64 24 # DBB01DR0 # CMP_CR0 65 25 # DBB01DR1 W ASY_CR 66 26 RW DBB01DR2 RW CMP_CR1 67 27 DBB01CR0 # 68 28 DCB02DR0 # 69 29 DCB02DR1 W 6A 2A DCB02DR2 RW 6B 2B DCB02CR0 # 6C 2C RW DCB03DR0 # TMP_DR0 6D 2D RW DCB03DR1 W TMP_DR1 6E 2E RW DCB03DR2 RW TMP_DR2 6F 2F RW DCB03CR0 # TMP_DR3 30 70 RW ACB00CR3 31 71 RW ACB00CR0 32 72 RW ACB00CR1 33 73 RW ACB00CR2 34 74 RW ACB01CR3 75 35 RW ACB01CR0 36 76 RW ACB01CR1 37 77 RW ACB01CR2 78 38 39 79 3A 7A 7B 3B 3C 7C 7D 3D 7E 3E 7F 3F Blank fields are Reserved and should not be accessed. PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 ASD20CR0 91 ASD20CR1 92 ASD20CR2 93 ASD20CR3 94 ASC21CR0 95 ASC21CR1 96 ASC21CR2 97 ASC21CR3 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 MUL1_X A9 MUL1_Y AA MUL1_DH AB MUL1_DL AC ACC1_DR1 AD ACC1_DR0 AE ACC1_DR3 AF ACC1_DR2 B0 RDI0RI B1 RDI0SYN B2 RDI0IS B3 RDI0LT0 B4 RDI0LT1 B5 RDI0RO0 B6 RDI0RO1 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW RW
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
W W R R RW RW RW RW RW RW RW RW RW RW RW
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
RL
RW # #
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CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
2. Register Reference
Register Map Bank 1 Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
40 00 RW RW PMA0_WA 41 01 RW RW PMA1_WA 42 02 RW RW PMA2_WA 43 03 RW RW PMA3_WA 44 04 RW RW PMA4_WA 45 05 RW RW PMA5_WA 46 06 RW RW PMA6_WA 47 07 RW RW PMA7_WA 48 08 RW 49 09 RW 4A 0A RW 4B 0B RW 4C 0C RW 4D 0D RW 4E 0E RW 4F 0F RW 50 10 RW RW PMA0_RA 51 11 RW RW PMA1_RA 52 12 RW RW PMA2_RA 53 13 RW RW PMA3_RA 54 14 RW RW PMA4_RA 55 15 RW RW PMA5_RA 16 56 RW RW PMA6_RA 17 57 RW RW PMA7_RA 18 58 19 59 1A 5A 1B 5B 1C 5C RW PRT7DM0 1D 5D RW PRT7DM1 1E 5E RW PRT7IC0 1F 5F RW PRT7IC1 20 60 RW RW DBB00FN CLK_CR0 21 61 RW RW DBB00IN CLK_CR1 22 62 RW RW DBB00OU ABF_CR0 23 63 RW AMD_CR0 64 24 DBB01FN RW CMP_GO_EN RW 65 25 DBB01IN RW CMP_GO_EN1 RW 66 26 RW DBB01OU RW AMD_CR1 27 67 RW ALT_CR0 68 28 DCB02FN RW 69 29 DCB02IN RW 6A 2A DCB02OU RW 2B 6B 6C 2C RW DCB03FN RW TMP_DR0 6D 2D RW DCB03IN RW TMP_DR1 6E 2E RW DCB03OU RW TMP_DR2 2F 6F RW TMP_DR3 30 70 RW ACB00CR3 31 71 RW ACB00CR0 32 72 RW ACB00CR1 33 73 RW ACB00CR2 34 74 RW ACB01CR3 35 75 RW ACB01CR0 36 76 RW ACB01CR1 37 77 RW ACB01CR2 78 38 39 79 7A 3A 3B 7B 7C 3C 3D 7D 7E 3E 3F 7F Blank fields are Reserved and should not be accessed. PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 ASD20CR1 92 ASD20CR2 93 ASD20CR3 94 ASC21CR0 95 ASC21CR1 96 ASC21CR2 97 ASC21CR3 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 RDI0RI B1 RDI0SYN B2 RDI0IS B3 RDI0LT0 B4 RDI0LT1 B5 RDI0RO0 B6 RDI0RO1 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
RW RW RW RW RW RW RW RW
USBIO_CR2 USB_CR1
C0 C1
RW #
RW RW RW RW RW RW RW
RW RW RW RW RW RW RW
C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 GDI_O_IN D1 GDI_E_IN D2 GDI_O_OU D3 GDI_E_OU D4 D5 D6 D7 D8 MUX_CR0 D9 MUX_CR1 DA MUX_CR2 DB MUX_CR3 DC OSC_GO_EN DD DE OSC_CR4 DF OSC_CR3 E0 OSC_CR0 E1 OSC_CR1 E2 OSC_CR2 E3 VLT_CR E4 VLT_CMP E5 E6 E7 E8 IMO_TR E9 ILO_TR EA BDG_TR EB ECO_TR EC MUX_CR4 ED MUX_CR5 EE EF F0 F1 F2 F3 F4 F5 F6 F7 CPU_F F8 F9 FA FB FC FD DAC_CR FE CPU_SCR1 CPU_SCR0 FF
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
# # # #
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW R
W W RW W RW RW
RL
RW # #
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3. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC TA 70oC and TJ 82oC. Figure 3-1. Voltage versus CPU Frequency
5.25
4.75 Vdd Voltage
lid ng Va rati n e io Op Reg
3.00
93 kHz CPUFrequency
12 MHz
24 MHz
The following table lists the units of measure that are used in this chapter. Table 3-1: Units of Measure
Symbol
o
Unit of Measure
Symbol W
Unit of Measure
C
degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts
dB fF Hz KB Kbit kHz k MHz M
A F H s V Vrms
mA ms mV nA ns nV
pA pF pp ppm ps sps
V
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3. Electrical Specifications
3.1
Symbol
Absolute Maximum Ratings
Description Min Typ Max Units
oC
Table 3-2. Absolute Maximum Ratings
Notes
TSTG
Storage Temperature
-55
25
+100
Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
TA Vdd VIO VIO2 IMIO IMAIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 -50 2000 -
- - - - - - - -
+85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 - 200
oC
V V V mA mA V mA Human Body Model ESD.
3.2
Symbol
Operating Temperature
Description Min Typ Max Units
o
Table 3-3. Operating Temperature
Notes
TA TAUSB TJ
Ambient Temperature Ambient Temperature using USB Junction Temperature
-40 -10 -40
- - -
+85 +85 +100
C
oC o
C
The temperature rise from ambient to junction is package specific. See "Thermal Impedance" on page 42. The user must limit the power consumption to comply with this requirement.
3.3
3.3.1
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-4. DC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
Vdd IDD5
Supply Voltage Supply Current, IMO = 24 MHz (5V)
3.0 -
- 14
5.25 27
V mA
See DC POR and LVD specifications, Table 315 on page 29. Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC TA 55 oC, analog power = off. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA 85 oC, analog power = off.
IDD3
Supply Current, IMO = 24 MHz (3.3V)
-
8
14
mA
ISB
Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a
-
3
6.5
A
ISBH
-
4
25
A
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled.
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3. Electrical Specifications
3.3.2
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-5. DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU RPD VOH
Pull-Up Resistor Pull-Down Resistor High Output Level
4 4 Vdd - 1.0
5.6 5.6 -
8 8 -
k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200 mA maximum combined IOL budget. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC.
VOL
Low Output Level
-
-
0.75
V
VIL VIH VH IIL CIN COUT
Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.1 - - - -
- - 60 1 3.5 3.5
0.8
V V
- - 10 10
mV nA pF pF
3.3.3
DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10C TA 85C, or 3.0V to 3.6V and -10C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-6. DC Full-Speed (12 Mbps) USB Specifications
Symbol USB Interface Description Min Typ Max Units Notes
VDI VCM VSE CIN IIO REXT VUOH VUOHI VUOL ZO VCRS
Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High-Z State Data Line Leakage External USB Series Resistor Static Output High, Driven Static Output High, Idle Static Output Low USB Driver Output Impedance D+/D- Crossover Voltage
0.2 0.8 0.8 - -10 23 2.8 2.7 - 28 1.3
- - - - - - - - - - -
- 2.5 2.0 20 10 25 3.6 3.6 0.3 44 2.0
V V V pF
A
| (D+) - (D-) |
0V < VIN < 3.3V. In series with each USB pin. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. 15 k 5% to Ground. Internal pull-up enabled. Including REXT Resistor.
V V V
V
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3. Electrical Specifications
3.3.4
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 3-7. 5V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA
Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - - - - 0.0 0.5 1.6 1.3 1.2 7.0 20 4.5 - - 10 8 7.5 35.0 - 9.5 Vdd Vdd - 0.5 mV mV mV
V/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias)
pA pF V
Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.
GOLOA
Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - - - - - - 65
-
-
dB
VOHIGHOA
High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - - - - 400 500 800 1200 2400 4600 80 - - - 0.2 0.2 0.5 800 900 1000 1600 3200 6400 - V V V V V V
A A A A A A
VOLOWOA
Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High
ISOA
Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High
PSRROA
Supply Voltage Rejection Ratio
dB
Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
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Table 3-8. 3.3V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA
Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only - - - - - 0.2 1.65 1.32 7.0 20 4.5 - 10 8 35.0 - 9.5 Vdd - 0.2 mV mV
V/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range
pA pF V
Gross tested to 1 A. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.
GOLOA
Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - - - - - 65
-
-
dB
VOHIGHOA
High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only - - - - - - 400 500 800 1200 2400 4600 80 - - - 0.2 0.2 0.2 800 900 1000 1600 3200 6400 - V V V V V V
A A A A A A
VOLOWOA
Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low
ISOA
Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High
PSRROA
Supply Voltage Rejection Ratio
dB
Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd.
3.3.5
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-9. DC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
VREFLPC ISLPC VOSLPC
Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset
0.2 - -
- 10 2.5
Vdd - 1 40 30
V
A
mV
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3.3.6
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-10. 5V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High
- - 0.5 - -
3 +6 - 0.6 0.6
12 - Vdd - 1.0 - - - -
mV
V/C
V

VOHIGHOB
High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High
0.5 x Vdd + 1.1 - 0.5 x Vdd + 1.1 -
V V
VOLOWOB
Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V
ISOB
Supply Current Including Bias Cell (No Load) Power = Low Power = High - - 53 1.1 2.6 64 5.1 8.8 - mA mA dB (0.5 x Vdd - 1.3) VOUT (Vdd 2.3).
PSRROB
Supply Voltage Rejection Ratio
Table 3-11. 3.3V DC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High
- - 0.5 - -
3 +6 1 1
12 - Vdd - 1.0 - - - -
mV
V/C
V

VOHIGHOB
High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.0 - 0.5 x Vdd + 1.0 - V V
VOLOWOB
Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High - - - - 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V
ISOB
Supply Current Including Bias Cell (No Load) Power = Low Power = High - 34 0.8 2.0 64 2.0 4.3 - mA mA dB (0.5 x Vdd - 1.0) VOUT (0.5 x Vdd + 0.9).
PSRROB
Supply Voltage Rejection Ratio
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3. Electrical Specifications
3.3.7
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 3-12. 5V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG - - - - - - - - - - - - - - - - -
Bandgap Voltage Reference AGND = Vdd/2a AGND = 2 x BandGap
a
1.28 Vdd/2 - 0.04 2 x BG - 0.048
1.30 Vdd/2 - 0.01 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000
1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018 0.034
V V V V V V V V V V V V V V V V V V
AGND = P2[4] (P2[4] = AGND = BandGapa
Vdd/2)a
P2[4] - 0.011 BG - 0.009
AGND = 1.6 x BandGap
a a
1.6 x BG - 0.022 -0.034
AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Vdd/2 + BG - 0.10
3 x BG - 0.06 2 x BG + P2[6] - 0.113 P2[4] + BG - 0.130 P2[4] + P2[6] - 0.133 3.2 x BG - 0.112
Vdd/2 + BG
3 x BG 2 x BG + P2[6] - 0.018 P2[4] + BG - 0.016 P2[4] + P2[6] - 0.016 3.2 x BG
Vdd/2 + BG + 0.10
3 x BG + 0.06 2 x BG + P2[6] + 0.077 P2[4] + BG + 0.098 P2[4] + P2[6]+ 0.100 3.2 x BG + 0.076
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Vdd/2 - BG - 0.04
BG - 0.06 2 x BG - P2[6] - 0.084 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.057
Vdd/2 - BG + 0.024
BG 2 x BG - P2[6] + 0.025 P2[4] - BG + 0.026 P2[4] - P2[6] + 0.026
Vdd/2 - BG + 0.04
BG + 0.06 2 x BG - P2[6] + 0.134 P2[4] - BG + 0.107 P2[4] - P2[6] + 0.110
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
Table 3-13. 3.3V DC Analog Reference Specifications
Symbol Description Min Typ Max Units
BG - - - - - - - - - - - - - - - - -
Bandgap Voltage Reference AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGapa AGND Column to Column Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
a
1.28 Vdd/2 - 0.03 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.075 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048
1.30 Vdd/2 - 0.01
1.32 Vdd/2 + 0.005
V V
P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000
P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034
V V V V
P2[4] + P2[6] - 0.009
P2[4] + P2[6] + 0.057
V
P2[4]- P2[6] + 0.022
P2[4] - P2[6] + 0.092
V
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V 0.02V.
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3. Electrical Specifications
3.3.8
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-14. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max Units Notes
RCT CSC
Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor)
- -
12.2 80
- -
k fF
3.3.9
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V or 3.3V at 25C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical Reference Manual for more information on the VLT_CR register. Table 3-15. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
Vdd Value for PPOR Trip (positive ramp) VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 V V V V V V V V V - - - 92 0 0 - - - mV mV mV - 2.82 4.39 4.55 - V V V - 2.91 4.39 4.55 - V V V
a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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3.3.10
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-16. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total) Flash Data Retention
a
- - 2.1 - - - Vdd - 1.0 50,000 1,800,000 10
15 - - - - - - - - -
30 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - -
mA V V mA mA V V - - Years Erase/write cycles per block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor.
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
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3.4
3.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-17. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO245V FIMO243V FIMOUSB5V FIMOUSB3V FCPU1 FCPU2 FBLK5 FBLK3 F32K1 Jitter32k Step24M Fout48M Jitter24M1 FMAX TRAMP
Internal Main Oscillator Frequency for 24 MHz (5V) Internal Main Oscillator Frequency for 24 MHz (3.3V) Internal Main Oscillator Frequency with USB (5V) Frequency locking enabled and USB traffic present. Internal Main Oscillator Frequency with USB (3.3V) Frequency locking enabled and USB traffic present. CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency (5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Peak-to-Peak Maximum frequency of signal on row input or row output. Supply Ramp Time
23.04 22.08 23.94 23.94 0.93 0.93 0 0 15 - - 46.08 - - 0
24 24 24 24 24 12 48 24 32 100 50 48.0 300 - -
24.96
a,b
MHz MHz MHz MHz MHz MHz MHz MHz kHz ns kHz MHz ps MHz
s
Trimmed for 5V operation using factory trim values. Trimmed for 3.3V operation using factory trim values. -10C TA 85C 4.35 Vdd 5.15 -0C TA 70C 3.15 Vdd 3.45
25.92b,c 24.06b 24.06b
24.96a,b 12.96
b,c
49.92a,b,d 25.92
b, d
Refer to the AC Digital Block Specifications.
64 -
49.92a,c
Trimmed. Utilizing factory trim values.
12.96 -
a. b. c. d.
4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules.
Figure 3-2. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
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3.4.2
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-18. AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO TRiseF TFallF TRiseS TFallS
GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF
0 3 2 10 10
- - - 27 22
12 18 18 - -
MHz ns ns ns ns
Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%
Figure 3-3. GPIO Timing Diagram
90% GPIO Pin O u tp u t Vo lta g e 10%
TR ise F TR ise S
TFallF TF a llS
3.4.3
AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -10C TA 85C, or 3.0V to 3.6V and -10C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-19. AC Full-Speed (12 Mbps) USB Specifications
Symbol Description Min Typ Max Units Notes
TRFS TFSS TRFMFS
Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF)
4 4 90 12 - 0.25%
- - - 12
20 20 111
ns ns %
For 50 pF load. For 50 pF load. For 50 pF load.
TDRATEFS Full-Speed Data Rate
12 + 0.25% Mbps
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3. Electrical Specifications
3.4.4
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 3-20. 5V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA
Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - - - - 3.9 0.72 0.62
s s s
TSOA
Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High - - - 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 - - - - - - - - - - - - - 100 5.9 0.92 0.72 - - - - - - - - - -
s s s
SRROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High V/s V/s V/s V/s V/s V/s MHz MHz MHz nV/rt-Hz
SRFOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High
BWOA
Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High
ENOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Table 3-21. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TROA
Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High - - - - 3.92 0.72
s s
TSOA
Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High - - 0.31 2.7 0.24 1.8 0.67 2.8 - - - - - - - - - 100 5.41 0.72 - - - - - - -
s s
SRROA
Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High V/s V/s V/s V/s MHz MHz nV/rt-Hz
SRFOA
Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High
BWOA
Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High
ENOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
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3. Electrical Specifications
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 3-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 3-5. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq (kHz)
1
10
100
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3. Electrical Specifications
3.4.5
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 3-22. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units s Notes 50 mV overdrive comparator reference set within VREFLPC.
TRLPC
LPC response time
-
-
50
3.4.6
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-23. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
Timer
Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture
50 - -
a
- - - - - -
- 49.92 25.92 - 49.92 25.92
ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
Counter
Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input
50a - -
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency 20 50
a
- - - - - - - - - - -
- - - 49.92 49.92 24.6 8.2 4.1 - 24.6 24.6
ns ns ns MHz MHz MHz MHz MHz ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V.
50a - - - - - 50a - -
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
3.4.7
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-24. AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT - -
Frequency for USB Applications Duty Cycle Power up to IMO Switch
23.94 47 150
24 50 -
24.06 53 -
MHz %
s
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3. Electrical Specifications
3.4.8
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-25. 5V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units s s s s Notes
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 - - - - - - - - - - - - 2.5 2.5 2.2 2.2 - - - - - - - -
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High V/s V/s V/s V/s MHz MHz kHz kHz
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High
BWOBSS
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High
BWOBLS
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High
Table 3-26. 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units s s s s Notes
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High - - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200 - - - - - - - - - - - - 3.8 3.8 2.6 2.6 - - - - - - - -
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High V/s V/s V/s V/s MHz MHz kHz kHz
SRFOB
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High
BWOBSS
Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High
BWOBLS
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High
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3. Electrical Specifications
3.4.9
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-27. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3
Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK
1 1 40 40 0 - - - -
- - - - - 10 30 - -
20 20 - - 8 - - 45 50
ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 Vdd 3.6
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3. Electrical Specifications
3.4.10
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, or 3.0V to 3.6V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 3-28. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Standard Mode Symbol Description Min Max Fast Mode Min Max Units Notes
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter.
0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 -
100 - - - - - - - - -
0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0
a
400 - - - - - - - - 50
kHz
s s s s s
ns
s s
ns
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Figure 3-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
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4. Packaging Information
This chapter illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package and solder reflow peak temperatures. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
4.1
Packaging Dimensions
Figure 4-1. 56-Lead (8x8 mm) QFN
001-12921 **
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4. Packaging Information
Figure 4-2. 68-Lead (8x8 mm x 0.89 mm) QFN
51-85214 *C
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.
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4. Packaging Information
Figure 4-3. 100-Ball (6x6 mm) VFBGA
51-85209 *B
Figure 4-4. 100-Lead (14x14 x 1.4 mm) TQFP
51-85048 *C
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4. Packaging Information
4.2
Thermal Impedance
Package Typical JA *
Table 4-1. Thermal Impedance for the Package
56 QFN** 68 QFN** 100 VFBGA * TJ = TA + POWER x JA
12.93 oC/W 13.05 oC/W 65 oC/W
** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
4.3
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Table 4-2. Solder Reflow Peak Temperature
Package Minimum Peak Temperature* Maximum Peak Temperature
56 QFN 68 QFN 100 VFBGA
240oC 240 C 240oC
o
260oC 260oC 260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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5. Development Tool Selection
This chapter presents the development tools available for all current PSoC device families including the CY8C24x94 family.
5.1
5.1.1
Software
PSoC DesignerTM
5.2
Development Kits
All development kits can be purchased from the Cypress Online Store.
At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http:// www.cypress.com under DESIGN RESOURCES >> Software and Drivers.
5.2.1
CY3215-DK Basic Development Kit
5.1.2
PSoC ExpressTM
The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:
PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples
As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress.
5.1.3
PSoC Programmer
Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer.
5.1.4
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items..
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5. Development Tool Selection
5.2.2
CY3210-ExpressDK PSoC Express Development Kit
5.3.3
CY3214-PSoCEvalUSB
The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes:
PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:
PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack
5.4
Device Programmers
All device programmers can be purchased from the Cypress Online Store.
5.4.1
CY3216 Modular Programmer
5.3
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store.
The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
5.3.1
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:
MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
5.4.2
CY3207ISSP In-System Serial Programmer (ISSP)
5.3.2
CY3210-PSoCEval1
The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:
CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:
Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
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5. Development Tool Selection
5.5
Accessories (Emulation and Programming)
Pin Package Flex-Pod Kita Foot Kitb Adapterc
Table 5-1. Emulation and Programming Accessories
Part #
CY8C24794 -24LFXI CY8C24894 -24LFXI
56 QFN 56 QFN
CY325024X94QFN CY325024X94QFN
CY325056QFN-FK CY325056QFN-FK
AS-56-28 AS-28-28-02SS6ENG-GANG
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
5.6
3rd-Party Tools
Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.
5.7
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/ an2323.
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6. Ordering Information
The following table lists the CY8C24x94 PSoC device's key package features and ordering codes. Table 6-1. CY8C24x94 PSoC Device's Key Features and Ordering Information
Analog Outputs 2 2 2 2 2 2 2 2 2 2 Analog Blocks Digital IO Pins Analog Inputs Digital Blocks Temperature Range
56 Pin (8x8 mm) QFN 56 Pin (8x8 mm) QFN (Tape and Reel) 56 Pin (8x8 mm) QFN 56 Pin (8x8 mm) QFN (Tape and Reel) 68 Pin OCD (8x8 mm) QFNa 68 Pin (8x8 mm) QFN 68 Pin (8x8 mm) QFN (Tape and Reel) 100 Ball OCD (6x6 mm) VFBGAa 100 Ball (6x6 mm) VFBGA 100 Pin OCD TQFPa
CY8C24794-24LFXI CY8C24794-24LFXIT CY8C24894-24LFXI CY8C24894-24LFXIT CY8C24094-24LFXI CY8C24994-24LFXI CY8C24994-24LFXIT CY8C24094-24BVXI CY8C24994-24BVXI CY8C24094-24AXI
16K 16K 16K 16K 16K 16K 16K 16K 16K 16K
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
4 4 4 4 4 4 4 4 4 4
6 6 6 6 6 6 6 6 6 6
50 50 49 49 56 56 56 56 56 56
48 48 47 47 48 48 48 48 48 48
No No Yes Yes Yes Yes Yes Yes Yes Yes
a. This part may be used for in-circuit debugging. It is NOT available for production.
6.1
Ordering Code Definitions
Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free BVX = VFBGA Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress
CY 8 C 24 xxx-SPxx
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XRES Pin
Ordering Code
Package
Flash (Bytes)
SRAM (Bytes)
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7. Sales and Company Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600 Web Sites: Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm
7.1
Revision History
CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC(R) Mixed-Signal Array Final Data Sheet
Table 6-1. CY8C24x94 Data Sheet Revision History
Document Title: Document Number: 38-12018
Revision ECN # Issue Date Origin of Change Description of Change
** *A *B *C
133189 251672 289742 335236
01.27.2004 NWJ See ECN See ECN See ECN SFV HMT HMT
New silicon and new document - Advance Data Sheet. First Preliminary Data Sheet. Changed title to encompass only the CY8C24794 because the CY8C24494 and CY8C24694 are not being offered by Cypress MicroSystems. Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2 MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs. Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP programming pinout notation. Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and specs. (Rext, IMO, analog output buffer...). Add new color and logo. Expand analog arch. diagram. Fix IO #. Update Electrical Specifications. Add USB temperature specifications. Make data sheet Final. Remove USB logo. Add URL to preferred dimensions for mounting MLF packages. Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to specs. Upgrade to CY Perform logo and update corporate address and copyright. Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs. Update Low Output Level maximum IOL budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash bank should be used for SROM operations. Add two new devices for a 68-pin QFN and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages for 68-pin QFN. Add OCD non-production pinouts and package diagrams. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to 56-pin QFN package diagram and update revision. Secure one package diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix pinout type-o per TestTrack. Add CapSense SNR requirement reference. Update figure standards. Update Technical Training paragraphs. Add QFN package clarifications and dimensions. Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword SNR reference. Add new 56-pin QFN spec.
Posting: None
*D *E *F *G *H
344318 346774 349566 393164 469243
See ECN See ECN See ECN See ECN See ECN
HMT HMT HMT HMT HMT
*I
561158
See ECN
HMT
*J
728238
See ECN
HMT
Distribution: External/Public
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7. Sales and Company Information
7.2
Copyrights and Code Protection
(c) Cypress Semiconductor Corporation. 2004-2007. All rights reserved. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.
February 15, 2007
Document No. 38-12018 Rev. *J
48
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